1. Field of the Invention
The present invention relates to a semiconductor device, particularly a capacitive element, having a metal-oxide-semiconductor (MOS) structure formed on a semiconductor substrate.
2. Description of the Prior Art
Capacitive elements formed on the surface of a semiconductor substrate are used in various semiconductor devices. Examples are a capacitive element for holding electric charge in a dynamic random-access memory (DRAM), a couple capacitive element connected crosswise to a bit line pair in a multi-level storage DRAM, and a capacitive element in an analog-to-digital (A-D) comparator. The capacitance of a couple capacitive element has an influence on the accuracy of a multi-level storage sensing operation. The capacitance of a capacitive element used in an A-D comparator has an influence on the accuracy of A-D conversion. Accordingly, these capacitive elements formed are required to have a highly accurate capacitance.
Capacitive elements generally have a metal-insulator-metal (MIM) structure and a metal-insulator-semiconductor (MIS) structure. A metal-oxide-semiconductor (MOS) structure as one MIS structure, in which the insulator is an oxide, can be fabricated by the same formation steps as a MOS field-effect transistor as a principal element constituting a semiconductor device. Therefore, a MOS structure has been most often used as a MOS capacitor.
A MOS structure often used as a MOS capacitor comprises a diffusion layer formed on the surface of a semiconductor substrate and having a conductivity type different from that of the semiconductor substrate, an oxide film (generally a silicon oxide film) formed on the surface of the diffusion layer, and a conductor layer formed on the silicon oxide film. The diffusion layer functions as one electrode, and the conductor layer functions as the other electrode. This MOS structure operates as a MOS capacitor when a voltage is applied between these two electrodes.
FIGS. 1A and 1B are a plan view and a sectional view showing the planar structure and the sectional structure, respectively, of a conventional MOS capacitor commonly used. In FIGS. 1A and 1B, reference numeral 101 denotes a P-type silicon substrate; 102, an N channel doped layer formed by lightly doping an N-type impurity such as phosphorus into the surface of the P-type silicon substrate 101; 103, a gate oxide film made of a silicon oxide film formed on the major surface of the P-type silicon substrate including the channel doped layer 102; 104, a first gate electrode formed on the gate oxide film 103 in the region of the channel doped layer 102 and made from polycrystalline silicon doped with an N-type impurity; and 105, a first N.sup.+ diffusion layer formed by heavily doping an N-type impurity in the major surface of the P-type silicon substrate 101 around the gate electrode 104. This first N.sup.+ diffusion layer 105 is formed by implanting ions of an impurity such as phosphorus at a high concentration by using the first gate electrode 104 as a mask and performing annealing to diffuse the phosphorus as an impurity. Consequently, the layer is heavily doped to a region deeper than the channel doped layer 102. Also, the first N.sup.+ diffusion layer 105 diffuses in the lateral direction due to annealing and enters slightly inside the outer peripheral portion of the first gate electrode 104. In this manner, a MOS capacitor is fabricated which has the first gate electrode 104 formed on the gate oxide film 103 as one electrode and the first N.sup.+ diffusion layer 105 formed below the gate oxide film 103 and connected to the channel doped layer 102 as the other electrode.
This MOS capacitor shows an operating characteristic as shown in FIG. 2 when a voltage is applied between the two electrodes. That is, when a gate voltage VG applied to the first gate electrode is higher than a reference voltage applied to the first N.sup.+ diffusion layer, i.e., when a positive voltage is applied, a storage state in which a negative electric charge in the channel doped layer 102 is accumulated in the surface portion is set, and a capacitance C1 takes a fixed value. When VG is shifted from a positive voltage to a negative voltage, the capacitance C1 is fixed until a predetermined negative voltage VGd. The value of VGd depends upon the work function of the first gate electrode, the impurity concentration in the channel doped layer, and the film thickness of the gate oxide film. When VG is further shifted to a negative voltage, a negative electric charge in the channel doped layer in the vicinity of the gate oxide film 103 is gradually pushed in the direction of depth, and a depletion layer having no free electric charge extends in the direction of depth on the surface of the channel doped layer 102. The formation of this depletion layer depends upon the impurity concentration in the channel doped layer 102, and the magnitude of the negative voltage applied to the gate oxide film and the gate electrode. When VG is further shifted to a predetermined negative voltage VGa or lower at which the width of the depletion layer reaches a maximum value, an inversion layer having a positive electric charge is formed on the surface of the channel doped layer 102, and the capacitance C1 takes a fixed value. As described above, when the N-type impurity concentration in the channel doped layer 102 is low, the full capacitance C1 of the MOS capacitor is obtained by connecting, in series, a capacitance Cox of the gate oxide film and a capacitance Cs1, which depends upon the gate voltage VG, of the depletion layer and the inversion layer, as shown in FIG. 3, and is represented by equation (1) below. EQU 1/C1=(1/Cox)+(1/Cs1) (1)
As the impurity concentration in the channel doped layer 102 increases, the depletion layer width decreases, and so the second term on the right side of equation (1) decreases. On the other hand, almost no depletion layer is formed in a region where the first gate electrode 104 and the first N.sup.+ diffusion layer 105 with a sufficiently high impurity concentration overlap each other with the gate oxide film 103 between them. Accordingly, the second term on the right side of equation (1) becomes a negligibly small value. The capacitance in this overlap region is represented only by the first term on the right side of equation (1), i.e., by the capacitance Cox of the gate oxide film.
As described above, in the MOS capacitor shown in FIGS. 1A and 1B in which the impurity concentration in the channel doped layer 102 is low and the channel doped layer 102 immediately below the first gate electrode 104 occupies a large area, the capacitance C1 of the MOS capacitor at negative voltages lower than VGd largely changes with applied voltage. This is a serious problem in a couple capacitance or a capacitive element used in an A-D comparator.
As one prior art for alleviating the above problem that the capacitance C1 of a MOS transistor lowers at negative voltages, a semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 1-146351.
FIGS. 4A and 4B are a plan view and a sectional view for explaining the planar structure and the sectional structure, respectively, of the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 1-146351. Note that a description of the same parts as in FIGS. 1A and 1B will be omitted. In FIGS. 4A and 4B, reference numerals 101 to 103 denote the same components as in the prior art shown in FIGS. 1A and 1B; 106, a rectangular second gate electrode serving as a first conductive layer; 107, rectangular apertures; and 108, a second N.sup.+ diffusion layer as an impurity region serving as a second conductive layer. In the second gate electrode 106, five apertures 107 are formed in each of the longitudinal and lateral directions. The second N.sup.+ diffusion layer 108 is formed in a region corresponding to the outer peripheral portion of the second gate electrode 106 around the channel doped layer 102 and is also formed in regions opposing the apertures 107. These are the big differences from the construction shown in FIGS. 1A and 1B. Generally, the second gate electrode 106 and the second N.sup.+ diffusion layer 108 are formed as follows. Note that the steps until the gate oxide film 103 is formed are the same as the structure shown in FIGS. 1A and 1B and a description thereof will be omitted.
After the gate oxide film 103 is formed, an electrode film made of a doped polycrystalline silicon film or the like is deposited on the entire surface. This electrode film is patterned to form the second gate electrode 106 having the apertures 107. Thereafter, the second gate electrode 106 is used as a mask to implant ions of an impurity such as phosphorus at a high concentration, forming an ion-implanted layer. The impurity is then diffused by annealing to form the second N.sup.+ diffusion layer 108. The result is a MOS capacitor having, as its two electrodes, the second gate electrode 106 and the second N.sup.+ diffusion layer 108 formed with the gate oxide film 103 between them.
In this MOS capacitor, the area of the second gate electrode 106 is the same as the area of the first gate electrode 104 in FIGS. 1A and 1B. However, the formation region of the second gate electrode 106 is larger because the apertures 107 are formed. On the other hand, the second N.sup.+ diffusion layer 108 is formed in the region corresponding to the outer peripheral portion of the second gate electrode 106 and the regions opposing the apertures 107. Therefore, the region of lateral diffusion .DELTA.x is also a high doped impurity layer, and the total area of these lateral diffusion regions is larger than the area in FIGS. 1A and 1B. That is, the ratio accounted for by the area of the channel region at a low impurity concentration immediately below the second gate electrode 106 is reduced, and this reduces the ratio of the second term depending on the gate voltage on the right side of equation (1). Consequently, the MOS transistor shows an operating characteristic with a high accuracy.
In the prior art shown in FIGS. 4A and 4B, the apertures 107 are formed in the second gate electrode 106, and the second N.sup.+ diffusion layer 108 is also formed in the regions of these apertures 107. Therefore, in the second N.sup.+ diffusion layer, the ratio of the area of the region of the channel doped layer 102 to the lateral diffusion regions is reduced, and this reduces a decrease in the capacitance C1 when a negative gate voltage is applied. However, this problem is not completely solved. That is, a fundamental problem is that when this MOS capacitor is used in a semiconductor device, the capacitance C1 is not fixed within the range of use voltages applied between the two electrodes of the MOS capacitor.
A method of solving this problem is to sufficiently increase the impurity concentration in the channel doped layer so that no depletion occurs. The impurity concentration in the channel doped layer 102 can be increased to be substantially the same as the impurity concentration in the first N.sup.+ diffusion layer 108. However, this gives rise to another problem when the fabrication process for increasing the impurity concentration in the channel doped layer 102 is taken into consideration.
The channel doped layer 102 can be formed before or after the formation of the gate oxide film 103. In the fabrication method by which the channel doped layer 102 is formed after the formation of the gate oxide film 103, in order to form the channel doped layer 102 only in a desired region, a resist pattern is formed by a lithography step, an N-type impurity such as phosphorus is doped by ion implantation, the resist is removed, and then polycrystalline silicon for forming the first gate electrode 104 is deposited. That is, various steps such as lithography and ion implantation are inserted between the gate oxidation step for forming the gate oxide film 103 and the step of depositing the polycrystalline silicon film serving as the first gate electrode 104. It is well known that the insulating properties of the gate oxide film 103 significantly deteriorate when these various steps are performed with the thin gate oxide film 103 exposed. The result is low reliability of the gate oxide film.
On the other hand, the fabrication method by which the channel doped layer 102 is formed before the formation of the gate oxide film 103 does not have the problem of a decrease in the reliability of the gate oxide film 103 as described above, since polycrystalline silicon serving as the first gate electrode 104 can be deposited immediately after the gate oxide film 103 is formed. However, when the channel doped layer 102 with a high impurity concentration is to be formed, it is necessary to perform gate oxidation after the impurity concentration is raised by increasing the ion implantation amount of an impurity such as phosphorus. This poses another problem in the oxidation of a silicon substrate having a heavily doped impurity layer on its surface.
FIG. 5 shows the film thickness increase ratio and the capacitance decrease ratio of a gate oxide film as functions of the ion implantation dose of phosphorus for forming the channel doped layer 102 when gate oxidation is performed in an oxygen atmosphere at 850.degree. C. The film thickness increase ratio is defined as (the thickness of the gate oxide film in the region of the channel doped layer)/(the thickness of the gate oxide film on the P-type silicon substrate not doped with an N-type impurity). The capacitance decrease ratio is defined as (the capacitance at gate voltage VG=-2 V)/(the capacitance at gate voltage VG=0 V). When the ion implantation dose is 5.times.10.sup.15 cm.sup.-2 or more, the capacitances at VG=-2 V and VG=0 V are nearly the same, so the capacitance of the MOS capacitor is independent of the gate voltage at least until the gate voltage is -2 V. However, the thickness of the gate oxide film on the surface of the channel doped layer formed with this ion implantation dose is 2.3 times as large as the thickness of the oxide film on the P-type silicon layer having no N-type impurity layer on its surface. It is also possible to determine the gate electrode area of the MOS transistor by which a desired capacitance is obtained by previously taking account of this increase in the thickness of the gate oxide film. As is apparent from FIG. 5, however, when the ion implantation dose is around 5.times.10.sup.15 cm.sup.-2, the gate oxide film thickness largely changes with slight changes in the ion implantation amount. This indicates the drawback that a process fluctuation has a large influence. Also, when a silicon substrate in the surface of which an N-type impurity is heavily doped is oxidized, the impurity diffuses outward during the oxidation. Consequently, the gate oxidation furnace is contaminated by the impurity such as phosphorus.